As is known in the art, large host computers (also referred to as application servers collectively referred to herein as “host computer/servers”) require large capacity data storage systems. These large host computer/servers generally include data processors which perform many operations on data transported to and from the host computer/server through peripherals including the data storage system.
One type of data storage system is a magnetic disks storage system. Here many disk drives are organized into separate sets of disk banks, and these banks are controlled and managed by “back-end” disk controllers (or directors). Also a set of “front-end” (directors) are provided by the storage system and are used by host computer/servers for physical attachment to the storage system. That is, data is stored in and retrieved from the bank of disk drives in such a way that the host computer/server merely thinks it is operating with its own local disk drive. One such system is described in U.S. Pat. No. 5,206,939, entitled “System and Method for Disk Mapping and Data Retrieval”, inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.
As described in such U.S. patent, the storage system may also include, in addition to the host computer/server controllers, (i.e., processors or directors) and disk controllers (sometimes also referred to as processors or directors), addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the host computer/server before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the host computer/server. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.
The host computer/server controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board (i.e., backplane). More particularly, disk controllers are mounted on disk controller printed circuit boards. The host computer/server controllers are mounted on host computer/server controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk directors, host computer/server directors, and cache memory printed circuit boards plug into the backplane.
As is also known in the art, it is desirable to provide accurate time information to each of the processors in the storage system. At present, crystal oscillators—one used upon each of the directors for purposes of basic operation and time keeping—are separate from one other. As such time status information remains incoherent between processing elements at the storage system's perspective. Time offset, skew, and drift can only be corrected using statistical methods by the processor elements. As will be discussed a mechanism is presented here to replace the statistical method with a deterministic one. This is especially useful for purposes of aggregating the transport of data across multiple physical I/O channels, referred to in the art as real-time parallel I/O.
Reference is also made to “Network Time Protocol (Version 3) Specification, Implementation and Analysis”, Network Working Group, David L. Mills University of Delaware March 1992.